This invention generally relates to integrated high-voltage switching circuitry. In particular, the invention relates to integrated high-voltage switching circuitry for use in conjunction with an array of elements. Such arrays include, but are not limited to, ultrasound transducer arrays, liquid crystal display pixel arrays, and so forth.
For the purpose of illustration, various embodiments of the invention will be described with reference to an ultrasound transducer array, e.g., the so-called xe2x80x9cmosaic annular arrayxe2x80x9d, for use in ultrasound imaging. A mosaic annular array employs the idea of dividing the active aperture of an ultrasound transducer into a mosaic of very small subelements and then forming annular elements from these subelements by interconnecting them with electronic switches. However, the geometry of the array elements is not limited to annular shapes. These array xe2x80x9celementsxe2x80x9d can be xe2x80x9cmovedxe2x80x9d electronically along the surface of the mosaic array to perform scanning by changing the switch configuration. Other element configurations permit beamsteering, which will provide the ability to acquire volumetric data sets. A configuration of multiple concentric annular elements provides optimal acoustic image quality by matching the element shapes to the acoustic phase fronts. The switches of the present invention are not limited to use in mosaic arrays, but rather could be used with standard ultrasound transducers.
Conventional ultrasound imaging systems comprise an array of ultrasonic transducers that are used to transmit an ultrasound beam and then receive the reflected beam from the object being studied. Such scanning comprises a series of measurements in which the focused ultrasonic wave is transmitted, the system switches to receive mode after a short time interval, and the reflected ultrasonic wave is received, beamformed and processed for display. Typically, transmission and reception are focused in the same direction during each measurement to acquire data from a series of points along an acoustic beam or scan line. The receiver is dynamically focused at a succession of ranges along the scan line as the reflected ultrasonic waves are received.
For ultrasound imaging, the array typically has a multiplicity of transducers arranged in one or more rows and driven with separate voltages. By selecting the time delay (or phase) and amplitude of the applied voltages, the individual transducers in a given row can be controlled to produce ultrasonic waves that combine to form a net ultrasonic wave that travels along a preferred vector direction and is focused in a selected zone along the beam.
The same principles apply when the transducer probe is employed to receive the reflected sound in a receive mode. The voltages produced at the receiving transducers are summed so that the net signal is indicative of the ultrasound reflected from a single focal zone in the object. As with the transmission mode, this focused reception of the ultrasonic energy is achieved by imparting separate time delay (and/or phase shifts) and gains to the signal from each receiving transducer. The time delays are adjusted with increasing depth of the returned signal to provide dynamic focusing on receive.
The quality or resolution of the image formed is partly a function of the number of transducers that respectively constitute the transmit and receive apertures of the transducer array. Accordingly, to achieve high image quality, a large number of transducers is desirable for both two- and three-dimensional imaging applications. The ultrasound transducers are typically located in a hand-held transducer probe that is connected by a flexible cable to an electronics unit that processes the transducer signals and generates ultrasound images. The transducer probe may carry both ultrasound transmit circuitry and ultrasound receive circuitry.
It is known to include high-voltage components in the transmit circuitry to drive the individual ultrasound transducers, while low-voltage, high-density digital logic circuitry is used to provide transmit signals to the high-voltage drivers. The high-voltage drivers typically operate at voltages of up to approximately 100 volts, while the low-voltage logic circuitry has an operating voltage on the order of 5 volts in the case of TTL logic. The high-voltage drivers may be fabricated as discrete components or as integrated circuits, while the low-voltage logic circuitry may be fabricated as a separate integrated circuit or combined with the high-voltage circuitry on a single chip. In addition to transmit circuitry including the high-voltage drivers and low-voltage logic circuitry, the transducer head may include low-noise, low-voltage analog receive circuitry. The low-voltage receive circuitry, like the transmit logic circuitry, typically has an operating voltage on the order of 5 volts, and may be a separate integrated circuit or may be fabricated with the low-voltage transmit logic circuitry as a monolithic integrated circuit.
In order to maximize the number of transducers to achieve high-quality ultrasound images, it is desirable to integrate as much circuitry as possible in as small a volume as possible to reduce the size and complexity of the circuitry, whether the circuitry be located within a transducer probe or in an electronics unit separate therefrom. In addition, some applications, for example, very high-frequency ultrasound imaging, require that transmit circuitry be located as close as possible to the transducers to avoid signal loading by a long cable.
In addition, the integrated circuit must include switches for coupling selected ultrasound transducers of the array with the associated high-voltage drivers during transmit and with associated receivers during receive. One proposed ultrasound transducer array that employs integrated high-voltage driving circuits is a so-called xe2x80x9cmosaic annular arrayxe2x80x9d. In a mosaic annular array ultrasound probe there is a need for both matrix and access switches that can withstand the high voltages used on transmit. At the same time, since the array contains upwards of 40,000 switches, low-power operation is an important consideration. In addition, it must be possible to cascade many such switches in series. Finally, the switch should have the ability to retain its state independent of additional logic, thereby simplifying the required digital circuitry and also enabling the use of different transmit and receive apertures.
Currently, ultrasound machines use commercially available high-voltage switch integrated circuits that are generally packaged in groups of eight switches per device. A representative patent for this technology is U.S. Pat. No. 4,595,847. Generally, this device uses high-voltage DMOS switches that are integrated back to back. This is well known in the prior art as a requirement due to the parasitic body diodes that are contained in the devices. [See, for example, xe2x80x9cUsing the Power MOSFET""s Integral Reverse Rectifier,xe2x80x9d Fragale et al., Proc. PowerCon 7: Seventh National Solid-State Power Conversion Conference, San Diego, Calif., March 1980.] An important feature of this device is the ability to tolerate high voltages on both of the signal terminals while floating the gate control terminal relative to this voltage. A level shifter is employed to allow the switch to operate in this manner.
An application similar to that of the present invention is driving a liquid crystal display (LCD). The LCD requires high voltages (100 V) but does not require high current. A solution to the LCD driver problem is disclosed by Doutreloigne et al. in a paper entitled xe2x80x9cA Versatile Micropower High-Voltage Flat-Panel Display Driver etc.xe2x80x9d and also in European Published Patent Application No. 1089433. This device also uses high-voltage DMOS switches; however, it uses a dynamically biased level shifter. The advantage of using a dynamically biased level shifter is that it does not dissipate static power. The technique of dynamic storage of control voltage is well known in the prior art and is most often found in dynamic shift registers and in dynamic RAM, which are prevalent in commercial electronics. In particular, U.S. Pat. No. 5,212,474 discloses a high-voltage level shifter that uses dynamic storage of voltage to effect a low-power and small-form factor device.
In U.S. Pat. No. 6,288,603, Zanuccoli et al. disclose a high-voltage bidirectional switch that operates in a similar fashion to that disclosed by Doutreloigne et al., with the improved ability to operate independent of supply voltages at the switch terminals. This device also uses a dynamic level shifter that stores a control voltage on the gate of the switch FET. The device is adapted for operation with a single NMOS device and goes to great length to make this possible.
There is a need in an ultrasound transducer array for both matrix and access switches that can withstand the high voltages used on transmit while consuming low power. It must be possible to cascade many such switches in series. Also, in a mosaic annular array, integrated high-voltage switching elements are required which are as small as possible in order to fit into the tight pitch between ultrasound transducers. Finally, these switches should have the ability to retain their state independent of additional logic and with controlled variation of ON resistance.
The present invention is directed to high-voltage switching circuits, devices incorporating high-voltage switching circuits and methods of programming high-voltage switching circuits. Although the disclosed embodiments are suitable for use in an ultrasound transducer array, the high-voltage switching circuits disclosed herein are not limited to ultrasound imaging applications.
One aspect of the invention is a method of operating a switch having ON and OFF states and having a parasitic gate capacitance, the switch comprising a pair of DMOS FETs having a shared gate terminal, the sources of the DMOS FETs being connected to each other and the drains of the DMOS FETs being connected to the input and output terminals of the switch respectively, and the shared gate terminal being connected to a drain of a programming transistor, the gate of the programming transistor receiving a gate voltage, the source of the programming transistor receiving a programming voltage, and the drains of the DMOS FETs being biased at a bias voltage level. The method comprises the following steps: (a) transitioning from a first level of the programming voltage to a second level of the programming voltage, the second level of the programming voltage being lower than the first level of the programming voltage and being higher than the bias voltage level by an amount sufficient to turn on the switch; and (b) transitioning from a first level of the programming transistor gate voltage to a second level of the programming transistor gate voltage, the first level of the programming transistor gate voltage being approximately equal to the first level of the programming voltage, and the second level of the programming transistor gate voltage being lower than the second level of the programming voltage by an amount sufficient to turn on the programming transistor, whereby the second level of the programming voltage is applied to the shared gate terminal of the switch via the programming transistor.
Another aspect of the invention is a circuit comprising: a switch having ON and OFF states and having a parasitic gate capacitance, the switch comprising a pair of DMOS FETs having a shared gate terminal, the sources of the DMOS FETs being connected to each other and the drains of the DMOS FETs being connected to the input and output terminals of the switch respectively, and biased at a bias voltage level; and a control circuit for turning the switch on and off, the control circuit comprising: a programming transistor having its drain connected to the shared gate terminal of the switch, its source connected to receive a programming voltage, and its gate connected to receive a programming transistor gate voltage; first circuitry for causing a first transition from a first level of the programming voltage to a second level of the programming voltage, the second level of the programming voltage being lower than the first level of the programming voltage and being higher than the bias voltage level by an amount sufficient to turn on the switch; and second circuitry for causing a second transition from a first level of the programming transistor gate voltage to a second level of the programming transistor gate voltage, the first level of the programming transistor gate voltage being approximately equal to the first level of the programming voltage, and the second level of the programming transistor gate voltage being lower than the second level of the programming voltage by an amount sufficient to turn on the programming transistor, whereby the second level of the programming voltage is applied to the shared gate terminal of the switch via the programming transistor.
A further aspect of the invention is a circuit comprising: a switch having ON and OFF states and having a parasitic gate capacitance, the switch comprising a pair of DMOS FETs having a shared gate terminal, the sources of the DMOS FETs being connected to each other and the drains of the DMOS FETs being connected to the input and output terminals of the switch respectively; a control circuit for turning the switch on and off, the control circuit comprising a first level shifter having an input terminal and an output terminal, and a programming transistor having its drain connected to the shared gate terminal of the switch, having its source connected to a first terminal from which the programming transistor draws current, and having its gate connected to receive a voltage derived from a voltage output by the first level shifter; and a resistance connected across the switch output terminal and a second terminal. The switch turns on in response to the following conditions: a first gate control voltage level is applied to the input terminal of the first level shifter that results in the programming transistor passing current, while first and second bias voltage levels are respectively applied to the first and second terminals to produce a switch gate-source voltage that turns the switch on.
Yet another aspect of the invention is a device comprising: a switch having ON and OFF states and having a parasitic gate capacitance, the switch comprising a pair of DMOS FETs having a shared gate terminal, the sources of the DMOS FETs being connected to each other and the drains of the DMOS FETs being connected to the input and output terminals of the switch respectively, and biased at a bias voltage level; and a control circuit for turning the switch on and off, the control circuit having first and second control states, each of the first and second control states being a function of a programming voltage and a programming gate voltage applied to different terminals of the control circuit. In the first control state of the control circuit, the programming voltage has a first voltage level and the programming gate voltage has a voltage level less than the first voltage level, resulting in the switch being on. In the second control state of the control circuit, the programming voltage has a second voltage level less than the first voltage level and the programming gate voltage has a voltage level less than the second voltage level, resulting in the switch being off.
A further aspect of the invention is a method of operating a high-voltage switching circuit, comprising the following steps: programming a first ON resistance value for tile high-voltage switching circuit under a first set of operating conditions, comprising a first value for a predetermined parameter, by applying a first programming voltage to a gate of the high-voltage switching circuit; determining that the parameter has changed from the first value to a second value under a second set of operating conditions; and programming a second ON resistance value for the high-voltage switching circuit under the second set of operating conditions by applying a second programming voltage different than the first programming voltage to the gate.
Yet another aspect of the invention is a method for programming high-voltage switching circuits, comprising the following steps: (a) manufacturing first and second high-voltage switching circuits; (b) determining a first gate-source voltage that causes the first high-voltage switching circuit to have a desired ON resistance; (c) determining a second gate-source voltage that causes the second high-voltage switching circuit to have the desired ON resistance, the first and second gate-source voltages being different; (d) programming a control circuit to provide a first gate voltage to the first high-voltage switching circuit, the first gate voltage being dependent on the results of step (b); and (e) programming the control circuit to provide a second gate voltage to the second high-voltage switching circuit, the second gate voltage being dependent on the results of step (c), wherein the first and second gate voltages are different but produce approximately the same ON resistances during operation of the first and second high-voltage switching circuits.
Other aspects of the invention are disclosed and claimed below.